1. Field of the Invention
The present invention relates a semiconductor memory device using a word line drive circuit system and, more particularly, to a DRAM (Dynamic Random Access Memory) capable of increasing an access speed.
2. Description of the Related Art
In a DRAM, as in other semiconductor memory devices, a memory address of data is designated by a row address signal and a column address signal. In general, the row and column address signals are serially input to a chip in a time division mode using the same input pin. For this reason, in order to check whether an address signal input from the address input pin is the row address signal or the column address signal, an RAS (Row Address Strobe) signal and a CAS (Column Address Strobe) signal are used.
In recent years, as an operating speed of a DRAM is increased, a key point for increasing an access speed is a decrease in time from when the RAS signal falls and the potential of a word line rises to when a memory cell is selected.
FIG. 1 shows a memory cell, a row decoder, and a word line drive circuit in a conventional DRAM wherein one memory cell is emphasized in a memory cell array MCA. A row address signal Add is supplied to a NAND circuit 102 serving as a part of a row decoder. An output signal from the NAND circuit 102 is supplied to a word line drive circuit 101. The word line drive circuit 101 is constituted by an inverter 108 and n-channel MOS transistors 109, 110, and 111. The input terminal of the inverter 108 is connected to the output terminal of the NAND circuit 102 and inverts an output signal from the NAND circuit 102. One end of the current path of the MOS transistor 109 is connected to the output terminal of the inverter 108, the other end is connected to the gate of the MOS transistor 110, and the gate of the MOS transistor 109 is connected to a power source Vcc. One end of the current path of the MOS transistor 110 is connected to receive a potential V.sub.WDRV, and the other end is connected to one end of the current path of the MOS transistor 111. The other end of the current path of the MOS transistor 111 is connected to a ground point Vss, and the gate of the MOS transistor 111 is connected to the output terminal of the NAND circuit 102. The connection point between the current paths of the MOS transistors 110 and 111 is connected to a word line WL. In the word line drive circuit 101, the MOS transistor 110 serves as a transistor for driving the word line WL.
A memory cell 100 is constituted by an n-channel MOS capacitor 106 and an n-channel MOS transistor 107 serving as a transfer gate. One end of the current path of the MOS transistor 107 is connected to a bit line BL, the other end is connected to one electrode of the MOS capacitor 106, and the gate of the MOS transistor 107 is connected to the word line WL. A reference potential such as a ground potential is applied to the other electrode of the MOS capacitor 106.
An operation of the circuit shown in FIG. 1 will be described below with reference to a timing chart of FIG. 2. FIG. 2 is the timing chart of the signals in the circuit shown in FIG. 1. When an RAS signal input from the outside of a chip falls, i.e., goes to low level ("L" level), an address signal input from an address pin at this time is recognized as the row address signal Add. A row of memory cells in a memory cell array MCA is designated and selected by this row address signal. At this time, assuming that the threshold voltage of the MOS transistor 109 is set to be V.sub.TH1 and that a power source voltage is set to be Vcc, a gate potential V.sub.G of the MOS transistor 110 for driving the word line WL becomes "Vcc-V.sub.TH1 " (to be referred to as "H.sup.- " level hereinafter). The potential V.sub.WDRV applied to one end of the current path of the MOS transistor 110 is increased from Vss to "Vcc+V.sub.TH2 " (V.sub.TH2 is a threshold voltage of the MOS transistor 107) or more. When the potential V.sub.WDRV is to be increased, the gate potential V.sub.G of the MOS transistor 110 is increased to a high potential by capacitive coupling of a parasitic capacitance between the source and gate. As a result, a potential (to be referred to as "H.sup.+ " level hereinafter) equal to or higher than "Vcc+V.sub.TH2 " is transferred to the word line WL. As described above, the potential at "H.sup.+ " level equal to or higher than the power source potential Vcc is applied to the word line WL, because a voltage applied to the capacitor 106 in the memory cell 100 must be reliably set at Vcc level.
However, the circuit system shown in FIG. 1 has the following drawbacks.
First, before the gate potential V.sub.G of the word line drive transistor 110 goes to "H".sup.- " level, when the potential V.sub.WDRV applied to one end of the current path of the transistor 110 begins to increase, it may be impossible to increase the potential of the word line WL to "H.sup.+ " level. For this reason, a sufficient time margin is required from the leading edge of the potential V.sub.WDRV after the RAS signal rises, thereby limiting a high speed operation.
Secondly, when the potential V.sub.WDRV is to be increased, since the gate potential V.sub.G of the word line drive transistor 110 is increased by capacitive coupling of a parasitic capacitance between the source and gate of the transistor 110, a potential difference between the source and gate is small. A time from when the potential of the word line WL begins to increase to when the potential reaches "H.sup.+ " level is long.
In order to solve the above problems, a well-known circuit having a word line drive transistor constituted by a p-channel MOS transistor is shown in FIG. 3.
The word line drive circuit 101 is constituted by n-channel MOS transistors 132 and 133 and p-channel MOS transistors 129 and 130 for driving a word line WL. One end of the current path of the MOS transistor 133 is connected to the output terminal of the NAND circuit 102, the other end is connected to one end of the current path of the MOS transistor 129 and the gate of the MOS transistor 130, and the gate of the MOS transistor 133 is connected to the power source Vcc. The gate of the MOS transistor 129 is connected to one end of the current path of the MOS transistor 130. The current path of the MOS transistor 132 is connected between one end of the current path of the MOS transistor 130 and the ground point Vss, and the gate of the MOS transistor 132 is connected to the output terminal of the NAND circuit 102. The connection point between the current paths of the MOS transistors 130 and 132 is connected to the word line WL. The other end of each of the current paths and back gates of the MOS transistors 129 and 130 are connected to the output terminal of a word line potential generating circuit 125 and receive a potential V.sub.WL. Assuming that the threshold voltage of the transfer gate transistor 107 in the memory cell 100 is set to be V.sub.TH2, the potential V.sub.WL is set to be a constant potential ("H.sup.+ " level) equal to or higher than "Vcc+V.sub.TH2 ".
An operation of the circuit shown in FIG. 3 will be described with reference to a timing chart of FIG. 4. When the RAS signal falls to "L" level, an input address signal is recognized as the row address signal Add, and an output from the NAND circuit 102 goes to "L" level. As a result, the gate potential V.sub.G of the MOS transistor 130 goes to "L" level, and the MOS transistor 130 is turned on. At this time, when the output from NAND circuit 102 goes to "L" level, the MOS transistor 132 is turned off. Since the word line potential V.sub.WL as a high potential is always applied from the word line potential generating circuit 125 to the MOS transistor 130, the potential of the word line WL is increased to the potential V.sub.WL, thereby turning off the MOS transistor 129.
As described above, in the circuit shown in FIG. 3, since the potential of the word line WL can be increased to a sufficiently high potential only by recognizing the row address signal Add, an access operation is performed at a speed higher than that of an arrangement using the circuit of FIG. 1. However, the circuit system shown in FIG. 3 has the following problems.
In general, the following fact is known. That is, when a high electric field of 4 to 6 MV/cm or more is applied to the source-gate or drain-gate path of a MOS element, a gate oxide film is heavily damaged, and long-time reliability of the MOS element is remarkably degraded. At present, as the MOS element is micropatterned, a gate oxide film tends to be thin. For this reason, in order to assure the long-time reliability of the gate oxide film, it is attempted to decrease a power source voltage of an LSI (Large Scale Integrated circuit) itself.
The feature of the circuit shown in FIG. 3 is described as follows. As described above, the high voltage V.sub.WL ("H.sup.+ " level) is always applied to the sources of the word line drive transistors 129 and 130 by the generating circuit 125 for generating the potential V.sub.WL for the word line WL. For this reason, the gate oxide films of the MOS transistors 129 and 130 are heavily damaged compared with that of the circuit shown in FIG. 1, and the long-time reliability of the element cannot easily obtained.